The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jan. 13, 2016
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, CN;

Inventor:

Yuanfu Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/01 (2006.01); H01L 51/10 (2006.01); H01L 51/40 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 51/00 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1222 (2013.01); H01L 27/127 (2013.01); H01L 27/323 (2013.01); H01L 27/3272 (2013.01); H01L 29/78621 (2013.01); H01L 29/78633 (2013.01); H01L 29/78678 (2013.01); H01L 29/78696 (2013.01); H01L 51/0023 (2013.01); H01L 51/102 (2013.01);
Abstract

An array substrate and a fabricating method thereof are disclosed. The array substrate has a transparent substrate, a buffer layer, a first/second gate pattern, a transparent insulating layer and a first/second polysilicon pattern. The buffer layer is located on first/second portions of the transparent substrate. The first/second gate patterns are formed on the buffer layer and located respectively on the first/second portions. The transparent insulating layer covers the first/second gate patterns and the buffer layer. The first/second polysilicon patterns are formed on the transparent insulating layer, and have neighboring first/second regions and neighboring third/fourth regions; the second/fourth regions are first/second lightly doped polysilicon regions respectively; the first region and the first gate pattern have an identical first patterning shape; and the third region and the second gate pattern have an identical second patterning shape. The array substrate has a simple process, low producing cost, and high product yield.


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