The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2016
Filed:
Mar. 29, 2016
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Hyung Ju Choi, Seoul, KR;
Assignee:
SK HYNIX INC., Icheon-Si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 25/065 (2006.01); H01L 23/04 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/065 (2013.01); H01L 23/041 (2013.01); H01L 23/3178 (2013.01); H01L 23/49827 (2013.01); H01L 23/552 (2013.01); H01L 24/48 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06582 (2013.01);
Abstract
A semiconductor package and a method for manufacturing the same are provided. The semiconductor package may include a package substrate and at least one chip disposed on a first surface of the package substrate. The semiconductor package may include a boundary wall attached to the package substrate to surround the chip. The semiconductor package may include at least one bonding wire coupling the boundary wall to the package substrate. The semiconductor package may include a conductive roof covering a top surface of the boundary wall and extended to cover the first surface of the package substrate and the at least one chip.