The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jul. 19, 2013
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Yoshinori Yokoyama, Tokyo, JP;

Kazuyo Endo, Tokyo, JP;

Jun Fujita, Tokyo, JP;

Shinnosuke Soda, Tokyo, JP;

Kazuyasu Nishikawa, Tokyo, JP;

Yoichi Nogami, Tokyo, JP;

Yoshitsugu Yamamoto, Tokyo, JP;

Akira Inoue, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/52 (2006.01); H01L 23/10 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/52 (2013.01); H01L 21/50 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/10 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.


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