The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Sep. 18, 2013
Applicant:

Fujitsu Semiconductor Limited, Yokohama, Kanagawa, JP;

Inventors:

Shoko Saito, Nagoya, JP;

Tomoyuki Okada, Akiruno, JP;

Kanji Takeuchi, Setagaya, JP;

Mitsufumi Naoe, Akiruno, JP;

Masahiko Minemura, Kawasaki, JP;

Yukihiro Sato, Akiruno, JP;

Yoshito Konno, Niiza, JP;

Yasuhiko Inada, Hachioji, JP;

Tomoaki Inaoka, Yokohama, JP;

Naoya Sashida, Kuwana, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 29/00 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 23/544 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/308 (2013.01); H01L 21/32139 (2013.01); H01L 23/522 (2013.01); H01L 23/544 (2013.01); H01L 24/05 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/05556 (2013.01);
Abstract

A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.


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