The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Apr. 15, 2014
Applicants:

Centre National DE LA Recherche Scientifique, Paris, FR;

Commissariat À L'énergie Atomique ET Aux Énergies Alternatives, Paris, FR;

Inventors:

Guillaume Prenat, Grenoble, FR;

Grégory Di Pendina, Echirolles, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 14/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 14/009 (2013.01); G11C 14/0072 (2013.01); G11C 14/0081 (2013.01); G11C 11/16 (2013.01); G11C 13/0002 (2013.01);
Abstract

The invention concerns a memory cell comprising: first and second resistive elements (), at least one of which can be programmed to adopt at least two resistive states (RRmax); the first resistive element () being coupled between a first storage node () and a first intermediate node (), the second resistive element () being coupled between a second storage node () and a second intermediate node (); a transistor () coupled between the first and second intermediate nodes; and a control circuit arranged to activate the transistor while a second supply voltage (VDD, GND) is being applied to the first or second storage node to generate a programming current in a selected direction through the first and second resistive elements in order to program the resistive state of at least one of the elements.


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