The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Feb. 14, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Keone Streicher, San Ramon, CA (US);

Martin Langhammer, Salisbury, GB;

Yi-Wen Lin, Glendale, CA (US);

Hyun Yi, San Jose, CA (US);

Assignee:

ALTERA CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01); G06F 7/499 (2006.01); G06F 7/485 (2006.01); G06F 7/487 (2006.01);
U.S. Cl.
CPC ...
G06F 7/485 (2013.01); G06F 7/483 (2013.01); G06F 7/4876 (2013.01); G06F 7/499 (2013.01);
Abstract

Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.


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