The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jul. 21, 2015
Applicants:

Stmicroelectronics SA, Montrouge, FR;

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Alain Chantre, Seyssins, FR;

Sébastien Cremer, Sassenage, FR;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); G02B 6/10 (2006.01); C03B 37/022 (2006.01); H01L 21/00 (2006.01); H01L 31/102 (2006.01); G02B 6/136 (2006.01); H01S 5/343 (2006.01); H01S 5/026 (2006.01); H01S 5/02 (2006.01); G02B 6/132 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/136 (2013.01); G02B 6/12004 (2013.01); G02B 6/132 (2013.01); G02B 6/4257 (2013.01); H01S 5/021 (2013.01); H01S 5/026 (2013.01); H01S 5/343 (2013.01); G02B 2006/121 (2013.01); G02B 2006/12121 (2013.01);
Abstract

A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.


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