The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Apr. 02, 2014
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

William E. Edwards, Ann Arbor, MI (US);

John M. Hall, Chelsea, MI (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); G01R 31/317 (2006.01); H04L 1/00 (2006.01); G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31713 (2013.01); G01R 31/31701 (2013.01); G06F 1/00 (2013.01); H04L 1/00 (2013.01); H04L 2201/00 (2013.01);
Abstract

An integrated circuit having normal and special operating modes includes a mode entry interlock () which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal () to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal () for receiving a disassociated software command to enter into the special operating mode, and mode control logic () for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.


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