The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Jun. 06, 2015
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Axel Thomsen, Austin, TX (US);

Alan L. Westwick, Austin, TX (US);

Ricky Setiawan, Singapore, SG;

Rex Wong Tak Ying, Singapore, SG;

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03K 5/003 (2006.01); H03M 1/66 (2006.01); H03M 1/00 (2006.01); H03M 1/74 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0607 (2013.01); H03K 5/003 (2013.01); H03M 1/002 (2013.01); H03M 1/66 (2013.01); H03M 1/00 (2013.01); H03M 1/747 (2013.01);
Abstract

Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.


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