The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Jun. 10, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Mustafa Ulvi Erdogan, Allen, TX (US);

Sridhar Ramaswamy, Plano, TX (US);

Bhavesh G. Bhakta, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/095 (2006.01); H03L 7/089 (2006.01); H03L 7/087 (2006.01); H04L 7/04 (2006.01); H03L 7/08 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03L 7/095 (2013.01); H03L 7/087 (2013.01); H03L 7/0807 (2013.01); H03L 7/089 (2013.01); H04L 7/04 (2013.01); H04L 7/033 (2013.01);
Abstract

A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.


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