The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Oct. 30, 2014
Applicant:

Trixell, Moirans, FR;

Inventor:

Laurent Charrier, Moirans, FR;

Assignee:

TRIXELL, Moirans, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); H03K 19/003 (2006.01); H03K 19/20 (2006.01); H04N 5/378 (2011.01); G11C 5/06 (2006.01); G11C 7/18 (2006.01); G11C 5/04 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00392 (2013.01); G11C 5/02 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/063 (2013.01); G11C 7/18 (2013.01); H03K 19/20 (2013.01); H04N 5/378 (2013.01); G11C 11/4097 (2013.01);
Abstract

An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising identification circuits comprises: N ordered inputs indexed i, connected to N outputs of the preceding block of same index; and N ordered outputs indexed i, connected to N inputs of the following block of same index; each input for i≠N of the current block connected by routing line indexed to output i+1 of the current block; last input N of the current block not connected to output of the current block; and first outputof the current block not connected to input of the current block; each block comprising: a connection pad; and N logic gates indexed i, each gate comprising first and second inputs and an output, N buses indexed i comprising a line through N blocks, and connected to output of a logic gate.


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