The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Jul. 07, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Gyeonghan Cha, Geoje-si, KR;

Han-Kyul Lim, Seoul, KR;

SungJun Kim, Suwon-si, KR;

Chaeryung Kim, Seoul, KR;

DongUk Park, Hwaseong-si, KR;

Younwoong Chung, Seongnam-si, KR;

JungMyung Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03K 3/86 (2006.01); G06F 1/10 (2006.01); H03K 5/13 (2014.01); H03K 5/135 (2006.01); H03K 5/14 (2014.01);
U.S. Cl.
CPC ...
H03K 3/86 (2013.01); G06F 1/10 (2013.01); H03K 5/131 (2013.01); H03K 5/135 (2013.01); H03K 5/14 (2013.01);
Abstract

A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.


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