The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Dec. 28, 2015
Applicant:

Epistar Corporation, Hsinchu, TW;

Inventors:

Chih-Kuang Yu, Chiayi, TW;

Hung-Yi Kuo, Taipei, TW;

Assignee:

EPISTAR CORPORATION, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/38 (2010.01); H01L 33/62 (2010.01); H01L 33/00 (2010.01); H01L 33/06 (2010.01); H01L 33/08 (2010.01); H01L 33/40 (2010.01); H01L 33/22 (2010.01); H01L 33/32 (2010.01); H01L 33/50 (2010.01); H01L 33/48 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 33/005 (2013.01); H01L 33/0079 (2013.01); H01L 33/06 (2013.01); H01L 33/08 (2013.01); H01L 33/22 (2013.01); H01L 33/32 (2013.01); H01L 33/382 (2013.01); H01L 33/405 (2013.01); H01L 33/502 (2013.01); H01L 33/486 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A light-emitting device includes a first epi-structure with a top surface and a bottom surface opposite to the top surface, a first metal element and a second metal element disposed on the bottom surface, a first through-via, a conductive element disposed on the top surface, and a phosphor layer disposed on the top surface and covering the conductive element. The first epi-structure includes a first doped semiconductor layer, a second doped semiconductor layer closer to the bottom surface than the first doped semiconductor layer, and a light-emitting layer disposed between the first and second doped semiconductor layers. The first through-via extends through the first doped semiconductor layer and the second doped semiconductor layer and is electrically connected to the first doped semiconductor layer and the second metal element. The conductive element is in a configuration to expose a portion of the top surface, and electrically connected to the first through-via.


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