The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Nov. 26, 2014
Applicant:

Sandisk Technologies, Inc., Plano, TX (US);

Inventor:

Nobuo Hironaga, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 27/11529 (2013.01);
Abstract

A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.


Find Patent Forward Citations

Hironaga, Nobuo. (2016). Set of stepped surfaces formation for a multilevel interconnect structure (U.S. Patent No. 9502429). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9502429

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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