The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Apr. 09, 2016
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Goro Sakamaki, Tokyo, JP;

Yuri Azuma, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 13/10 (2006.01); G09G 3/20 (2006.01); G06F 13/40 (2006.01); G09G 3/36 (2006.01); G06F 13/42 (2006.01); G06F 7/76 (2006.01); G06F 13/20 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2096 (2013.01); G06F 7/768 (2013.01); G06F 9/4806 (2013.01); G06F 13/10 (2013.01); G06F 13/102 (2013.01); G06F 13/20 (2013.01); G06F 13/4013 (2013.01); G06F 13/4063 (2013.01); G06F 13/4221 (2013.01); G09G 3/36 (2013.01); G09G 2360/10 (2013.01);
Abstract

The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.


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