The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
Sep. 16, 2011
Ray Ruey-hsien HU, Milpitas, CA (US);
Andy L. Lee, San Jose, CA (US);
David Lewis, Toronto, CA;
Tony Ngai, Saratoga, CA (US);
Haiming Yu, Pleasanton, CA (US);
Hao-yuan Howard Chou, San Jose, CA (US);
Ray Ruey-Hsien Hu, Milpitas, CA (US);
Andy L. Lee, San Jose, CA (US);
David Lewis, Toronto, CA;
Tony Ngai, Saratoga, CA (US);
Haiming Yu, Pleasanton, CA (US);
Hao-Yuan Howard Chou, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.