The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Jan. 12, 2015
Applicant:

Dmitry Petrov, Nepean, CA;

Inventor:

Dmitry Petrov, Nepean, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/157 (2006.01); G05F 1/56 (2006.01);
U.S. Cl.
CPC ...
G05F 1/56 (2013.01); H02M 3/157 (2013.01);
Abstract

A method and voltage regulator comprises a generator that generates an error difference between a reference and regulated voltage. A clocked ADC samples the voltage as a digital stream. A DAC converts the stream to analog signal(s). A current source driven by the signal(s) generate(s) the regulated voltage. The generator may be an op-amp or comparator comprising a buffer and/or a latch. The N-bit ADC may be a Σ-Δ modulator or N 1-bit ADC latches. The N-bit DAC may comprise 1-bit DACs comprising a switched-capacitor summer and a one stage RC LPF. Sampling the error up-converts flicker noise to the clock frequency which the DAC filters out. The current source may comprise N transistors with gates driven by a signal and sources tied to an independent power supply. Each signal may be weighted by a DAC weight. The apparatus may comprise a decoupling capacitor between the regulated voltage and ground.


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