The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Aug. 13, 2014
Applicants:

Murata Manufacturing Co., Ltd., Nagaokakyo-shi, Kyoto-Fu, JP;

National Institute for Materials Science, Tsukuba-shi, Ibaraki-ken, JP;

Inventors:

Sakyo Hirose, Nagaokakyo, JP;

Naoki Ohashi, Tsukuba, JP;

Hideki Yoshikawa, Tsukuba, JP;

Assignees:

MURATA MANUFACTURING CO., LTD., Nagaokakyo-Shi, Kyoto-Fu, JP;

NATIONAL INSTITUTE FOR MATERIALS SCIENCE, Tsukuba-Shi, Ibaraki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 45/00 (2006.01); H01L 29/47 (2006.01); H01L 29/872 (2006.01); H01L 29/861 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/08 (2013.01); H01L 29/24 (2013.01); H01L 29/47 (2013.01); H01L 29/8615 (2013.01); H01L 29/872 (2013.01); H01L 45/1253 (2013.01); H01L 45/1266 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/1608 (2013.01); H01L 45/1625 (2013.01);
Abstract

A resistance switching device having a high resistance variation ratio, an excellent response characteristic, an excellent resistance memory characteristic (retention characteristics) and an excellent repeat resistance. The resistance switching device comprises an n-type oxide semiconductor and first and second electrodes which are disposed so as to interpose at least a part of the n-type oxide semiconductor therebetween wherein a Schottky junction which provides resistance variation/memory characteristics by the application of voltage having different polarities between the first and second electrodes is formed at an interface between the n-type oxide semiconductor and the first electrode; and the first electrode is positioned such that it is in contact with the n-type oxide semiconductor, and has a lower layer which is formed from Au oxide or a Pt oxide or Au or Pt containing oxygen having the thickness of 1-50 nm.


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