The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2016
Filed:
May. 30, 2014
Texas Instruments Incorporated, Dallas, TX (US);
Henry Litzmann Edwards, Garland, TX (US);
Toan Tran, Rowlett, TX (US);
Jeffrey R. Debord, Dallas, TX (US);
Ashesh Parikh, Frisco, TX (US);
Bradley David Sucher, Murphy, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.