The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

May. 30, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Paul A. Nygaard, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/525 (2006.01); H01L 27/112 (2006.01); H01L 21/8234 (2006.01); G11C 17/16 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 17/16 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 23/5252 (2013.01); H01L 29/8611 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate insulator. The memory cell also comprises a bulk region of a first conductivity type in contact with a first side of the thin gate insulator. The memory cell also comprises a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator. The memory cell also comprises a source region of a second conductivity type in contact with the bulk region at a junction. The polysilicon gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator. The junction forms a diode for the memory cell. The bulk region can be in an active layer of a semiconductor on insulator structure.


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