The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Jan. 06, 2014
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Michael Lee, Saratoga, CA (US);

Takuji Yamamoto, San Jose, CA (US);

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/473 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G02B 6/4268 (2013.01); G02B 6/4274 (2013.01); H01L 23/473 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); G02B 6/4249 (2013.01); H01L 23/13 (2013.01); H01L 23/49827 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/00015 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may have a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface. The recess may be formed in the substrate and defined by the third surface and the orthogonal surface. The first conductive vias may pass from the second surface to the first surface. The second conductive vias may pass from the second surface to the third surface.


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