The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2016
Filed:
Dec. 19, 2014
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventor:
Trent S. Uehling, New Braunfels, TX (US);
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/03 (2006.01); H01L 23/48 (2006.01); H01K 3/10 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/31053 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 2924/0002 (2013.01);
Abstract
By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.