The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Sep. 13, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Andrew Currid, Alameda, CA (US);

Franck Diard, Saint Contest, FR;

Chenghuan Jia, Fremont, CA (US);

Parag Kulkarni, Pune, IN;

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/28 (2006.01); G06F 13/00 (2006.01); G06T 1/20 (2006.01); G09G 5/36 (2006.01); G06F 9/46 (2006.01); G06F 3/14 (2006.01); G06F 9/455 (2006.01); G06F 9/50 (2006.01); G09G 3/00 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 3/1438 (2013.01); G06F 9/46 (2013.01); G09G 5/363 (2013.01); G06F 9/455 (2013.01); G06F 9/5077 (2013.01); G09G 3/003 (2013.01); G09G 2360/06 (2013.01); G09G 2370/022 (2013.01);
Abstract

A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.


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