The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2016
Filed:
Aug. 12, 2014
Aniruddha Gupta, Ghaziabad, IN;
Akshay K. Pathak, Noida, IN;
Garima Sharda, Ghaziabad, IN;
Nidhi Sinha, New Delhi, IN;
Aniruddha Gupta, Ghaziabad, IN;
Akshay K. Pathak, Noida, IN;
Garima Sharda, Ghaziabad, IN;
Nidhi Sinha, New Delhi, IN;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.