The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Sep. 10, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Burt Lee Price, Apex, NC (US);

Yeshwant Nagaraj Kolla, Wake Forest, NC (US);

Dhaval Rajeshbhai Shah, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 1/30 (2006.01); G05F 1/46 (2006.01); H01L 21/66 (2006.01); G01R 19/00 (2006.01); G01R 31/30 (2006.01);
U.S. Cl.
CPC ...
G05F 1/46 (2013.01); H01L 22/30 (2013.01); G01R 19/003 (2013.01); G01R 31/3004 (2013.01);
Abstract

Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.


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