The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Nov. 23, 2015
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventors:

Sheau Jiung Lee, Saratoga, CA (US);

Yilei Li, Los Angeles, CA (US);

Wei-Han Cho, Los Angeles, CA (US);

Mau-Chung Frank Chang, Los Angeles, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 27/34 (2006.01); H04L 27/36 (2006.01); H04L 27/38 (2006.01); H04L 7/033 (2006.01); H04L 27/00 (2006.01);
U.S. Cl.
CPC ...
H04L 27/3455 (2013.01); H04L 7/0331 (2013.01); H04L 27/362 (2013.01); H04L 27/364 (2013.01); H04L 27/3872 (2013.01); H04L 2027/0022 (2013.01); H04L 2027/0028 (2013.01); H04L 2027/0055 (2013.01); H04L 2027/0067 (2013.01);
Abstract

A chip-to-chip communications circuit which is particularly well-suited for short range wired RF communication from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. During a phase calibration cycle, a phase adjustment controller in the transmitter interoperates with a phase adjustment controller in the receiver, to adjust a phase locked-loop (PLL) circuit to correct for the phase delay arising in response to signal propagation between transmitter and receiver.


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