The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Jan. 19, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Devesh P. Singh, Bijnor, IN;

Firas N. Abughazaleh, Austin, TX (US);

Anand Kumar Sinha, Noida, IN;

Sanjay K. Wadhwa, Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/089 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0891 (2013.01); H03L 7/099 (2013.01);
Abstract

A phase-locked loop (PLL) for generating an oscillating signal includes a frequency bounding circuit. When a frequency of the oscillating signal is greater than a first threshold value, which is greater than a maximum normal operational frequency of the PLL, the frequency bounding circuit forces a charge pump to discharge a loop filter until the oscillating signal frequency is less than a second threshold value that is within the normal operational frequency range of the PLL. When the frequency of the oscillating signal is less than a third threshold value, which is less than a minimum normal operational frequency of the PLL, the frequency bounding circuit forces the charge pump to charge the loop filter until the oscillating signal frequency is greater than a fourth threshold value that is within the normal operational frequency range of the PLL.


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