The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Jul. 08, 2014
Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US);
Sarma Vrudhula, Chandler, AZ (US);
Niranjan Kulkarni, Tempe, AZ (US);
Arizona Board of Regents on behalf of Arizona State University, Scottsdale, AZ (US);
Abstract
A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.