The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

May. 15, 2014
Applicant:

AU Optronics Corp., Hsin-Chu, TW;

Inventors:

Wei-Li Lin, Hsin-Chu, TW;

Che-Wei Tung, Hsin-Chu, TW;

Chia-Heng Chen, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORP., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); H03K 19/003 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00384 (2013.01); G09G 2310/0286 (2013.01); G11C 19/28 (2013.01);
Abstract

A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.


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