The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Apr. 27, 2016
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 5/135 (2006.01); H03K 19/20 (2006.01); H03K 19/003 (2006.01); H03K 19/096 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/135 (2013.01); H03K 19/00315 (2013.01); H03K 19/096 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01);
Abstract
A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller C-elements are connected to the clock and selection lines and first and second logic gates. First and second delay cells are connected to the clock lines and the second and fourth Muller C-elements. A first AND gate is connected to the first clock line, the first Muller C-element, and the first delay cell. A second AND gate is connected to the second delay cell, the third Muller C-element, and the second clock line, and an OR gate is connected to the first and second AND gates.