The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Feb. 10, 2015
Applicants:
Inayat Ali, Jabalpur, IN;
Puneet Dodeja, Delhi, IN;
Sachin Jain, New Delhi, IN;
Inventors:
Assignee:
FREESCALE SEMICONDUCTOR,INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 3/017 (2006.01); H03K 23/00 (2006.01); H03K 21/02 (2006.01); H03K 21/10 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); H03K 23/002 (2013.01); H03K 21/00 (2013.01); H03K 21/026 (2013.01); H03K 21/10 (2013.01); H03K 23/00 (2013.01);
Abstract
A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.