The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Jul. 28, 2015
Applicant:
Powerchip Technology Corporation, Hsinchu, TW;
Inventors:
Assignee:
Powerchip Technology Corporation, Hsinchu, TW;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/0223 (2013.01); H01L 21/02247 (2013.01); H01L 21/02318 (2013.01); H01L 21/0337 (2013.01); H01L 21/28273 (2013.01); H01L 21/31111 (2013.01); H01L 21/02252 (2013.01);
Abstract
A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly dielectric, a control gate and a metal layer on a substrate, forming a conformal liner on the gate stack structure, covering a mask layer on the liner, where the mask layer is lower than the metal layer so that a portion of the liner is exposed, and performing a nitridation treatment to transform the exposed liner into a nitrided liner, so that at least the portion of the metal layer in the gate stack structure is covered by the nitrided liner.