The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Oct. 01, 2015
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Hyun Min Lee, Gyeonggi-do, KR;

Han Woo Cho, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2409 (2013.01); H01L 27/224 (2013.01); H01L 43/02 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1246 (2013.01); H01L 45/1253 (2013.01); H01L 45/144 (2013.01); H01L 45/1683 (2013.01);
Abstract

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer.


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