The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Sep. 04, 2015
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Byoung-Gue Min, Daejeon, KR;

Sang Choon Ko, Daejeon, KR;

Jong-Won Lim, Daejeon, KR;

Hokyun Ahn, Daejeon, KR;

Hyung Sup Yoon, Daejeon, KR;

Jae Kyoung Mun, Daejeon, KR;

Eun Soo Nam, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/48 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/02365 (2013.01); H01L 21/28 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.


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