The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

May. 01, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventor:

Masaaki Nishijima, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 7/38 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/861 (2006.01); H01L 49/02 (2006.01); H03K 3/01 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 27/0629 (2013.01); H01L 28/60 (2013.01); H01L 29/2003 (2013.01); H01L 29/7787 (2013.01); H01L 29/861 (2013.01); H03H 7/38 (2013.01); H03K 3/01 (2013.01);
Abstract

A semiconductor device includes a semiconductor chip, a dielectric substrate, and bonding wires. The dielectric substrate includes wiring patterns formed on a surface and a ground metal layer formed on a back side. The semiconductor chip includes an active element and a drain pad that is connected to an output end of the active element. Wiring pattern is formed at a position closer to the drain pad than wiring pattern, wiring pattern and the ground metal layer constitute a first capacitative element, and wiring pattern and the ground metal layer constitute a second capacitative element. The drain pad is connected to wiring pattern through bonding wire, and connected to wiring pattern through bonding wire. Bonding wire and the first capacitative element constitute a high-pass matching circuit.


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