The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2016
Filed:
Jun. 16, 2015
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Tae Seung Kim, Dallas, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76813 (2013.01); H01L 21/76807 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 2924/0002 (2013.01);
Abstract
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The via-first process may be a partial-via-first process or a full-via-first process. A trench mask for a wide interconnect line which is at least twice as wide as a dual damascene via in the wide interconnect line may have a dielectric slot adjacent to the dual damascene via. The dual damascene via is laterally separated from the dielectric slot by no more than half a width of the dual damascene via.