The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Apr. 24, 2014
Applicant:

Gigadevice Semiconductor (Beijing) Inc., Beijing, CN;

Inventors:

Hong Hu, Beijing, CN;

Linkai Wang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/34 (2006.01); G11C 16/16 (2006.01); G11C 16/14 (2006.01); G11C 16/28 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/28 (2013.01); G11C 16/3477 (2013.01); G11C 16/107 (2013.01); G11C 16/3436 (2013.01);
Abstract

Disclosed are non-volatile memory erasure method and device for solving the problem of unnecessary time expenditure and complex process of the current erasure operation. The method comprises: after receiving an erasure instruction, performing a pre-reading verification on the target erasure area corresponding to the erasure instruction; if the pre-reading verification passes, then performing an erasure operation on the target erasure area; if not, then performing pre-programming verification on the target erasure area, and after the pre-programming verification passes, performing the erasure operation on the target erasure area. The method of the present application can eliminate the unnecessary pre-programming verification process while ensuring the target erasure area is in a full-erasure state before the erasure operation, thus saving erasure time and simplifying the erasure process.


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