The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Apr. 27, 2012
Applicants:

Craig Warner, Irving, TX (US);

Gary Gostin, Plano, TX (US);

Matthew D Pickett, San Francisco, CA (US);

Inventors:

Craig Warner, Irving, TX (US);

Gary Gostin, Plano, TX (US);

Matthew D Pickett, San Francisco, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 12/08 (2016.01); G06F 13/16 (2006.01); G06F 12/02 (2006.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0833 (2013.01); G06F 12/0238 (2013.01); G06F 12/0866 (2013.01); G06F 12/122 (2013.01); G06F 13/1673 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/312 (2013.01); G06F 2212/621 (2013.01); G06F 2212/69 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A method of shielding a memory device () from high write rates comprising receiving instructions to write data at a memory container (), the memory controller () composing a cache () comprising a number of cache lines defining stored data, with the memory controller (), updating a cache line in response to a write hit in the cache (), and with the memory controller (), executing the instruction to write data in response to a cache miss to a cache line within the cache () in which the memory controller () prioritizes for writing to the cache () over writing to the memory device ().


Find Patent Forward Citations

Loading…