The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Jul. 09, 2012
Applicants:

Craig M. Hill, Warrenton, VA (US);

Andrew T S Pomerene, Leesburg, VA (US);

Inventors:

Craig M. Hill, Warrenton, VA (US);

Andrew T S Pomerene, Leesburg, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H01L 27/06 (2006.01); H01L 21/82 (2006.01); G02B 6/136 (2006.01); G02B 6/132 (2006.01);
U.S. Cl.
CPC ...
G02B 6/12 (2013.01); G02B 6/12004 (2013.01); H01L 21/82 (2013.01); H01L 27/0617 (2013.01); G02B 6/132 (2013.01); G02B 6/136 (2013.01);
Abstract

A method for fabricating electronic and photonic devices on a semiconductor substrate using complementary-metal oxide semiconductor (CMOS) technology is disclosed. A substrate is initially patterned to form a first region for accommodating electronic devices and a second region for accommodating photonic devices. The substrate within the first region is thicker than the substrate within the second region. Next, an oxide layer is formed on the substrate. The oxide layer within the first region is thinner than the oxide layer within the second region. A donor wafer is subsequently placed on top of the oxide layer. The donor substrate includes a bulk silicon substrate, a sacrificial layer and a silicon layer. Finally, the bulk silicon substrate and the sacrificial layer are removed from the silicon layer such that the silicon layer remains on the oxide layer.


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