The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Aug. 26, 2014
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Asad A. Bawa, Cedar Park, TX (US);

Benjamin A. Marrou, Austin, TX (US);

Christopher Ng, Austin, TX (US);

Michael R. Seningen, Austin, TX (US);

Mihir S. Sabnis, Austin, TX (US);

Zameeruddin Mohammed, Austin, TX (US);

Yi Zhao, Austin, TX (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318552 (2013.01); G01R 31/3177 (2013.01); G01R 31/318541 (2013.01); G01R 31/318563 (2013.01); G01R 31/318575 (2013.01);
Abstract

A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.


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