The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

May. 21, 2015
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Juan Echeverri Escobar, Eindhoven, NL;

Surendra Guntur, Eindhoven, NL;

Manvi Agarwal, Eindhoven, NL;

Rinze Ida Mechtildis Peter Meijer, Herkenbosch, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3193 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/31937 (2013.01); H03K 3/0375 (2013.01);
Abstract

An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal, wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.


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