The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
Feb. 05, 2015
Min Cheol Shin, Daejeon, KR;
Jae Hyun Lee, Daejeon, KR;
Doo Hyung Kang, Daejeon, KR;
Jun Beom Seo, Daejeon, KR;
Woo Jin Jeong, Daejeon, KR;
Min Cheol Shin, Daejeon, KR;
Jae Hyun Lee, Daejeon, KR;
Doo Hyung Kang, Daejeon, KR;
Jun Beom Seo, Daejeon, KR;
Woo Jin Jeong, Daejeon, KR;
Korea Advanced Institute of Science and Technology, Daejeon, KR;
Abstract
A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.