The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Aug. 28, 2014
Applicant:

University of Central Florida Research Foundation, Inc., Orlando, FL (US);

Inventors:

Ahmadreza Amirahmadi, Orlando, FL (US);

Haibing Hu, Orlando, FL (US);

Issa Batarseh, Orlando, FL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 7/5383 (2007.01); H02M 7/5387 (2007.01); H02M 1/08 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 7/53873 (2013.01); H02M 1/083 (2013.01); H02M 2001/0058 (2013.01); Y02B 70/1491 (2013.01);
Abstract

A power inverter combination includes a half-bridge power inverter including first and second semiconductor power switches receiving input power having an intermediate node therebetween providing an inductor current through an inductor. A controller includes input comparison circuitry receiving the inductor current having outputs coupled to first inputs of pulse width modulation (PWM) generation circuitry, and a predictive control block having an output coupled to second inputs of the PWM generation circuitry. The predictive control block is coupled to receive a measure of Vin and an output voltage at a grid connection point. A memory stores a current control algorithm configured for resetting a PWM period for a switching signal applied to control nodes of the first and second power switch whenever the inductor current reaches a predetermined upper limit or a predetermined lower limit.


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