The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

May. 27, 2014
Applicant:

Kaneka Corporation, Osaka-shi, Osaka, JP;

Inventors:

Daisuke Adachi, Settsu, JP;

Hisashi Uzu, Settu, JP;

Assignee:

KANEKA CORPORATION, Osaka-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/18 (2006.01); H01L 31/0747 (2012.01); H01L 31/0216 (2014.01); H01L 31/0224 (2006.01); H01L 31/048 (2014.01);
U.S. Cl.
CPC ...
H01L 31/1884 (2013.01); H01L 31/02168 (2013.01); H01L 31/022425 (2013.01); H01L 31/022466 (2013.01); H01L 31/048 (2013.01); H01L 31/0747 (2013.01); H01L 31/1804 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

Provided is a solar cell including a photoelectric conversion section having a first principal surface and a second principal surface, and a collecting electrode formed on the first principal surface of photoelectric conversion section. The photoelectric conversion section includes a semiconductor-stacked portion including a semiconductor junction, a first electrode layer which is a transparent electrode layer formed on the first principal surface side of the semiconductor-stacked portion, and a second electrode layer formed on the second principal surface side of the semiconductor-stacked portion. The collecting electrode includes a first electroconductive layer and a second electroconductive layer. In the manufacturing method, an insulating layer is formed on the first electrode layer, and the electrode layer exposed to the surface of the insulating layer-non-formed region is removed to eliminate a short circuit between the first and second electrode layers. The second electroconductive layer is formed by plating.


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