The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
Dec. 09, 2013
Applicant:
Boe Technology Group Co., Ltd., Beijing, CN;
Inventors:
Hyun Sic Choi, Beijing, CN;
Hui Li, Beijing, CN;
Zhiqiang Xu, Beijing, CN;
Yoon Sung Um, Beijing, CN;
Assignee:
BOE Technology Group Co., Ltd., Beijing, CN;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/1343 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78648 (2013.01); G02F 1/1368 (2013.01); G02F 1/134363 (2013.01); G02F 1/136227 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 27/1288 (2013.01); H01L 29/41733 (2013.01); G02F 2001/134372 (2013.01);
Abstract
A array substrate is disclosed. The array substrate includes: a substrate (); and a first gate metal layer (), a first gate insulating layer (), a semiconductor layer () and a source-drain electrode layer () disposed in this order on the substrate from bottom to top. The array substrate () further includes a second gate insulating layer () disposed on the source-drain electrode layer (); and a second gate metal layer () disposed on the second gate insulating layer (). A method of manufacturing an array substrate is also disclosed.