The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Nov. 14, 2013
Applicant:

Tower Semiconductor Ltd., Migdal Haemek, IL;

Inventors:

Sagy Levy, Zichron-Yaakov, IL;

Sharon Levin, Haifa, IL;

Noel Berkovitch, Rishon LeZion, IL;

Assignee:

Tower Semiconductor Ltd., Migdal Haemek, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/32 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/32 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823462 (2013.01); H01L 21/823814 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 29/0634 (2013.01); H01L 29/0653 (2013.01); H01L 29/0878 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01); H01L 29/66689 (2013.01); H01L 21/26586 (2013.01); H01L 21/324 (2013.01); H01L 29/086 (2013.01); H01L 29/402 (2013.01);
Abstract

A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field 'bump' oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard 'bump' mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.


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