The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

May. 28, 2014
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Weihai Bu, Shanghai, CN;

Jin Kang, Shanghai, CN;

Yong Chen, Shanghai, CN;

Xinpeng Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 21/0228 (2013.01); H01L 21/02181 (2013.01); H01L 21/28194 (2013.01); H01L 21/31122 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 29/517 (2013.01); H01L 29/66477 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01);
Abstract

Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening.


Find Patent Forward Citations

Loading…