The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Mar. 02, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Yuhei Yoshimoto, Hyogo, JP;

Kazuhiko Shimakawa, Osaka, JP;

Ken Kawai, Osaka, JP;

Ryotaro Azuma, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0002 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 29/021 (2013.01); G11C 29/026 (2013.01); G11C 29/028 (2013.01); G11C 29/70 (2013.01); H01L 27/2409 (2013.01); H01L 27/2481 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); G11C 7/062 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0073 (2013.01); G11C 2213/56 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01);
Abstract

A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.


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