The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Nov. 05, 2013
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

G. Glenn Henry, Austin, TX (US);

Terry Parks, Austin, TX (US);

Rodney E. Hooker, Austin, TX (US);

John D. Bunda, Austin, TX (US);

Brent Bean, Austin, TX (US);

Assignee:

VIA TECHNOLOGIES, INC., New Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 9/44 (2006.01); G06F 9/26 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 9/26 (2013.01); G06F 9/30145 (2013.01); G06F 9/30174 (2013.01);
Abstract

A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores ('core memory'). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores ('uncore memory'). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.


Find Patent Forward Citations

Loading…