The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

May. 02, 2014
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

John Zinn, Canonsburg, PA (US);

Brett Diamond, Pittsburgh, PA (US);

Jochen Hoffmann, Reutlingen, DE;

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); H04R 31/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00246 (2013.01); H04R 31/00 (2013.01); B81B 2201/0257 (2013.01); B81C 2201/0132 (2013.01); H04R 2201/003 (2013.01);
Abstract

Systems and methods are disclosed for manufacturing a CMOS-MEMS device (). A partial protective layer () is deposited on a top surface of a layered structure to cover a circuit region. A first partial etch is performed from the bottom side of the layered structure to form a first gap () below a MEMS membrane () within a MEMS region of the layered structure. A second partial etch is performed from the top side of the layered structure to remove a portion of a sacrificial layer between the MEMS membrane and a MEMS backplate () within the MEMS region. The second partial etch releases the MEMS membrane so that it can move in response to pressures. The deposited partial protective layer prevents the second partial etch from etching a portion of the sacrificial layer positioned within the circuit region of the layered structure and also prevents the second partial etch from damaging the CMOS circuit component ().


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